(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to increase the performance of semiconductor device via use of more conductive metal structures, and lower dielectric constant, insulator layers.
(2) Description of the Prior Art
The continuing objectives of the semiconductor industry has been to increase the performance of semiconductor devices, while still maintaining, or reducing, the cost of these same semiconductor devices. The use of sub-micron features, or micro-miniaturization, used for semiconductor devices, has allowed the performance and cost objectives to be aggressively addressed. Devices with smaller features result in a reduction of performance degraded capacitances, evidenced by the higher performing metal oxide semiconductor field effect transistor, (MOSFET), devices, fabricated with sub-quarter micron channel lengths. In addition the use of sub-micron features result in a smaller semiconductor chip, however still possessing the same, or greater, device densities, than larger size semiconductor chips, fabricated using larger features. This allows more semiconductor chips to be realized from a specific size substrate, thus reducing the cost of a specific semiconductor chip.
Micro-miniaturization has in part, been accomplished via advances in specific semiconductor disciplines, such as photolithography, and dry etching. The use of more advanced exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images to be routinely achieved in photoresist layers. In addition, the development of more advanced dry etching tools, and processes, have allowed the sub-micron images, in overlying photoresist layers, to be successfully transferred to underlying conductive and insulating materials, used for the fabrication of semiconductor devices. However, in addition to the advances in semiconductor fabrication disciplines, specific structural developments, as well as material upgrades, are still needed to continue to improve device performance and lower cost.
The use of copper interconnect structures, exhibiting lower resistivity than aluminum, or tungsten counterparts, and the use of low dielectric constant, (low k), materials, such as hydrogen silsesquioxane, (HSG), or fluorinated silicate glass, (FSG), such as silicon oxyfluoride, have been used to decrease RC, (resistance--capacitance), delays. The more conductive copper interconnect structures, with increased electromigration resistance, compared to aluminum based counterparts, allow narrower metal interconnect structures to be used. However the definition of copper structures, using conventional photolithographic and dry etching procedures, can prove difficult when defining narrow metal interconnect structures, therefore the use of damascene metal structures, avoiding the difficulties encountered with conventional patterning procedures, has gained attention. This invention will describe a process in which a copper damascene structure, (single, or dual damascene), is embedded in a two level, composite insulator layer, with each component of the two level, composite insulator layer, having a low dielectric constant. The two levels of the composite insulator layer, are separated by a thin, silicon oxynitride layer, used as an etch stop layer, when forming the upper, wide diameter opening, of a dual damascene pattern, in the top level of composite insulator layer. In addition each level of the composite insulator layer, is comprised with two dielectric layers, each being a low k material. This is used to optimize capacitance, as well as to allow the use of an underlying HSQ layer, with a dielectric constant of about 2.8, to be integrated into the fabrication sequence, residing underlying a protective FSG layer, which in addition also features a low dielectric constant. Prior art, such as Fiordalice et al, in U.S. Pat. No. 5,578,523, as well as Lin, in U.S. Pat. No. 5,753,967, describe the use of low k dielectric constant layers, with a hard mask used between these layers. However those prior arts do not describe the use of two levels of low k dielectric constant layers, which each low k dielectric constant layer, a composite layer, comprised of two low k layers, each needed to achieve both capacitance objectives, as well as reducing fabrication complexities.